Samsung will launch 3D AI chip packaging technology SAINT to compete with TSMC

【Lansheng Technology News】On Sunday, Samsung plans to launch three technologies under the SAINT brand - SAINT S, which vertically stacks SRAM memory chips and CPUs; SAINT D, which involves vertical packaging of processors such as CPUs, GPUs and DRAM storage; and SAINT L, which stacks application processors. (AP).

Current 2.5D packaging technology, in most cases, assembles different types of chips side by side horizontally.

Sources say that some of Samsung's new technologies, including SAINT S, have passed verification tests. However, Samsung will launch its commercial service next year after further testing with customers.

Leading chipmakers such as TSMC, Samsung and Intel are competing fiercely for advanced packaging technology that can integrate different semiconductors or vertically interconnect multiple chips. Advanced packaging technologies allow multiple devices to be combined and packaged into a single electronic device.

Packaging technology can improve semiconductor performance without shrinking nanometer dimensions through ultra-fine processing, which is technically challenging and requires more time.

The global advanced chip packaging market is expected to grow from $44.3 billion in 2022 to $66 billion in 2027, according to consulting firm Yole Intelligence. Of the $66 billion, 3D packaging is expected to account for about a quarter, or $15 billion.

The technology has been growing rapidly, in line with the growth of generative artificial intelligence (such as ChatGPT), which requires semiconductors that can process large amounts of data quickly. The current mainstream in the industry is 2.5D packaging, which places chips as close as possible to reduce data bottlenecks.

TSMC, the world's largest contract chip manufacturer, is also a leader in the global advanced packaging market, with a decade-old 2.5D packaging technology.

TSMC is testing and upgrading its 3D chip-to-chip stacking technology SoIC for its customers, including Apple Inc. and Nvidia Corp. TSMC said in July that it would invest NT$90 billion (US$2.9 billion) to build a new domestic advanced packaging plant.

Earlier this month, Taiwan's United Microelectronics Corporation (UMC), the world's third largest foundry, launched a wafer-to-wafer (W2W) 3D IC project to provide customers with efficient integration of memories and processors using silicon stacking technology. cutting-edge solutions.

UMC said its W2W 3D IC project, in collaboration with packaging companies such as ASE, Winbond Electronics, Faraday and Cadence Design Systems, is an ambitious undertaking that aims to leverage 3D chip integration technology to meet the specific requirements of edge AI applications.

Since the launch of 2.5D packaging technology H-Cube in 2021, Samsung, the world's second largest foundry company, has been accelerating the development of its chip packaging technology. Samsung said the 2.5D packaging technology allows logic chips or high-bandwidth memory (HBM) to be stacked on a silicon interposer in a small size. The South Korean company said in April that it was offering turnkey packaging services, handling the entire process from chip production to packaging and testing. Samsung adopts new SAINT technology aimed at improving the performance of artificial intelligence chips for data centers and mobile APs with on-device AI capabilities.